Terabyte Bandwidth Initiative

The Rambus Terabyte Bandwidth Initiative reflects Rambus' ongoing commitment to innovation in cutting-edge performance memory architectures to enable tomorrow's most exciting gaming and graphics products. Targeting a terabyte per second (TB/s) of memory bandwidth (1 terabyte = 1,024 gigabytes) from a single System-on-Chip (SoC), Rambus has pioneered new memory technologies capable of signaling at 20 gigabits per second (Gbps) while maintaining best-in-class power efficiency. In order to enable the transition from current generation memory architectures, Rambus has developed innovations that support both single-ended and differential memory interfaces in a single SoC package design with no additional pins. The patented Rambus innovations that enable this breakthrough performance, unmatched power efficiency and multi-modal functionality include: 32X Data Rate – Enables high data rates while maintaining a low frequency system clock. Fully Differential Memory Architecture (FDMA) – Improves signal integrity and reduces power consumption at high-speed operation. FlexLink™ Command/Address (C/A) – Reduces the number of pins required for the C/A link. FlexMode™ Interface – Provides multi-modal functionality, either single-ended or differential in a single SoC package design with no additional pins. These innovations offer increased performance, higher and scalable data bandwidth, area optimization, enhanced signal integrity, and multi-modal capability for gaming, graphics and multi-core computing applications. With these innovations and others developed through the Terabyte Bandwidth Initiative, Rambus will provide the foundation for future memory architectures over the next decade. Background